Category: ARM
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Overview
Advanced RISC Machines(ARM) are becoming most popular day by day. The cores are providing handsome support to many direct applications. ARM provides optimization in all fields...whether its calculations or its memory access and memory alignment are bound when it comes to optimization.... ARM has different instructions to access a BYTE (8-bits), a HALF WORD (16-bits) and a WORD (32-bit). So, to get 8-bit or 32-bit from memory ARM uses only one instruction! Highly efficient! All high level language compilers provide some directives so that programmer can instruct compiler about the instruction usage. This optimizes code and enhances performance.
Till now everything is smooth then where the memory alignment arises?
Till ARMv4 architecture, it’s assumed that address given for fetching contents is memory aligned...a 32-bit data fetch should have address aligned to 32-bit and so on. As guessed correctly the problem is only for 32-bit and 16-bit data fetching. ARM ignores lower 2-bits of address if the data fetch is 32-bit, and ignores lower 1-bit if data fetch is 16-bit. So, in all if the address is not properly aligned then data fetch will be erroneous.
Why address is not aligned?
Data types known to compiler are automatically adjusted for faster memory access.
But, user code which gets address during run time, or user assigned memory address can cause unaligned access.
Let’s take an example:
WORD * wPtr = (WORD *) 0x00000001;
This declaration will give a unaligned WORD access resulting wrong data fetch.
Is there any alternative?
Yes. But at a price of more instructions!
The compiler can be instructed not to use optimized memory op-codes.
E.g. Above declaration will be converted into four memory fetches...i.e. four fetches of 8-bit memory to form a 32-bit data.
Compiler directives
Use following directives for GCC “-mshort-load-bytes” and “-mno-short-load-words”.
References
http://gcc.gnu.org/onlinedocs/gcc-3.3.6/gcc/ARM-Options.html
http://www.arm.com/
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