Simple Makefile

Category: Makefile
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This is an example how to write Makefile for cross-compiling a test application named test.c.
The Makefile would look like

1 CC = arm-linux-gcc
2 CFLAGS =
3 OBJECTS = test.o
4
5 test.o : test.c
6        $(CC) $(CFLAGS) -o $(OBJECTS) test.c
7
8  clean:
9        rm *.o


Working:
Line 1: Specifies a compiler name. (If required provide absolute path)
Line 2: Specifies any additional compilation flags like include directories etc.
Line 3: Specifies object file name.
Line 5: Defines that test.o depends on test.c, so if test.c is modified execute the command below
Line 6: Compilation command, it is expanded as :
           arm-linux-gcc -o test.o test.c
           Here we are compiling and linking so test.o is an executable for the ARM platform.
Line 8: Defines rule for clean.
Line 9: Defines command for cleaning / removing object files

Execution:
To run the Makefile, just type make. 

Caution:
- Makefile should be named as Makefile.
- Makefile has rules based on indentation. Here Line 6 and Line 9 need a TAB before command.
- If TAB is missing on Line 6 the make would return error: Makefile:6: *** missing separator. Stop

Reference:
http://www.delorie.com/djgpp/doc/ug/larger/makefiles.html
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